RF devices constructed from Group III-V semiconductor materials, such as GaAs or GaAs alloys, are commonly employed in wireless communication systems. Such RF devices may include RF power amplifiers, low noise amplifiers, switches, and other similar integrated circuits. Optimum performance makes it desirable that the resistance of the conductors that connect the circuit elements of the RF devices to bonding pads be as low as possible. This property commonly indicates the use of a thick layer of gold (Au), typically deposited by a plating process, as the material of the conductors. The combination of relatively challenging base device transistor vertical dimensions plus relatively small lateral dimensions leads to manufacturing challenges. Such challenges can be mitigated by the use of a process architecture in which the gold conductors are located on the substantially planar surface of an interlayer dielectric (ILD) layer, and vias extending through the ILD layer provide connections between the gold conductors and one or more layers of metallization of the underlying circuitry. In an example, the material of the ILD layer is bisbenzocyclobutene (BCB). The ILD layer and the conductors are then covered by a thick passivation layer. This approach undesirably creates large stress mismatches between the ILD layer, the gold conductors, and the passivation layer. Stress mismatches can compromise the hermeticity of the passivation, which can impair the reliability of the semiconductor device when the device is exposed to moisture.
FIG. 1 is a cross-sectional view showing a portion of an example 10 of a conventional Group III-V semiconductor device having a thick, plated-gold conductor on the surface of an interlayer dielectric layer. Device 10 includes a substrate 12 of gallium arsenide (GaAs) or a GaAs alloy. Circuit elements 14 (not individually shown) are located in and on substrate 12. A first metal layer 16 covers substrate 12 and is patterned to define conductors (not individually shown) that selectively interconnect the circuit elements. The material of first metal layer 16 is typically gold (Au). In some implementations, first metal layer 16 additionally includes clad layers of such metals as titanium (Ti) or platinum (Pt) on one or both of its surface facing substrate 12 and its surface remote from substrate 12. An interlayer dielectric (ILD) layer 18 covers the circuit elements and first metal layer 16 to provide a fully or partially planarized surface. Typical materials of ILD layer 18 include BCB, polyimide, and polybenzoxazole (PBO).
A via 22 extends through ILD layer 18. A second metal layer 24 covers ILD layer 118. Second metal layer 24 includes an interconnect 26 that extends through via 22 to first metal layer 16. Second metal layer 24 is additionally patterned to define conductors that extend across the surface of ILD layer 18. The material of second metal layer 24 is typically gold deposited by a plating process. A thick passivation layer 30 of dielectric material covers second metal layer 24 and the portions of ILD layer 18 exposed by the patterning of the second metal layer. Semiconductor device 10 includes passivation layer 30 to improve its resistance to moisture.
In a conventional semiconductor device having the structure just described, cracks 34 can form in passivation layer 30 at the corners 32 where the passivation layer follows the contour changes resulting from the presence of conductors 28 of the surface of ILD 18. Cracks 34 result in a loss of hermeticity that undesirably degrades the moisture reliability of the semiconductor device. FIG. 2 is a scanning electron microscope image showing a portion of an example of conventional semiconductor device 10. The image clearly shows a crack in the passivation layer at the corner between the ILD layer and the side of the conductor defined in the second metal layer.
Accordingly, what is needed is an architecture that allows a Group III-V semiconductor device to use thick plated gold conductors to without compromising the hermeticity of the passivation layer.